1. Field of the Invention
The present invention relates to a semiconductor device including a plurality of circuits connected to one another.
2. Description of the Related Art
FIG. 3 shows a circuit configuration of a semiconductor device. In the circuit configuration shown in FIG. 3, a signal is transmitted from a first inverter 101 to a second inverter 102. The second inverter 102 is a load for the first inverter 101. The first inverter 101 is a driver for the second inverter 102. A resistance 103 and a parasitic capacitance 104 are present between the first and second inverters 101 and 102. The resistance 103 and the parasitic capacitance 104 are inevitably generated when the inverters 101 and 102 are connected to each other.
FIG. 4 is a timing diagram illustrating signal inputs to and outputs from the first and second inverters 101 and 102. As can be understood from FIG. 4, when a signal 111 is input to the first inverter 101, a signal 112 is output from the first inverter 101. After a delay time period T, a signal 113 is input to the second inverter 102. A signal 114 is output from the second inverter 102. The delay time period T1 represents a delay time period of the entire circuit shown in FIG. 3. In this example, the delay time period T1 is determined based on the time when a signal which is input to or output from the inverter 101 or 102 rises or falls to 50% of the maximum level.
Such a time delay is determined in accordance with, for example, the resistance 103 and the parasitic capacitance 104. The resistance 103 and the parasitic capacitor 104 include, for example, an ON-resistance of an output transistor, a resistance of interconnects, and an input capacitance of an input transistor. Where the resistance 103 is R and the capacitance of the parasitic capacitance 104 is C, the delay time period T is represented by expression (1). EQU T=C.multidot.R (1)
In the case where the value R of the resistance 103 and the value C of the parasitic capacitance 104 are mostly determined by the interconnect between the first and second inverters 101 and 102, the delay time period T is represented by expression (2) where the length of the interconnect is L, the resistance of the interconnect per unit length is R0, and the capacitance of the interconnect per unit length is C0. EQU T=LR0.multidot.LC0=L.sup.2 .multidot.R0.multidot.C0 (2)
As can be understood from expression (2), the delay time period T of the interconnect is influenced by the resistance R connected to the interconnect in series and the capacitance C connected to the interconnect in parallel. Unless the resistance R0 and the capacitance C0 change, the delay time period T is extended as length L of the interconnect is extended.
When such a time delay caused in accordance with the length of the interconnect occurs in, for example, an LSI including multiple-stage circuits, the delay time period is multiplied at each circuit stage. Accordingly, the total delay time period of the entire circuit is excessively long, which prevents the circuit from operating at a higher rate.
In a semiconductor device such as an LSI, an extension in the delay time period caused by an interconnect is significant and the delay time period need be shortened. Conventionally, in order to lower the resistance of the interconnect, a material having a lower resistance is used for the interconnect, or a multiple-layer interconnect is used to avoid lengthy connections over extended distances and to shorten the required length of the interconnect. However, these solutions raise the cost of the semiconductor device and are not necessarily preferable.
FIG. 5 is an exemplary circuit configuration of a conventional semiconductor device. Such a circuit configuration disadvantageously extends and disperses the delay time period as described below. The circuit configuration shown in FIG. 5 includes a first circuit 121, a plurality of second circuits (six in this example) 122-1 through 122-6 (collectively referred to as "second circuits 122"), a plurality of first interconnects 123-1 through 123-4 (collectively referred to as "first interconnects 123"), a plurality of second interconnects 124-1 through 124-4 (collectively referred to as "second interconnects 124") for respectively connecting the circuits 122-1 through 122-6 to the first interconnects 123-1 through 123-4, and a plurality of third interconnects 125-1 through 125-4 (collectively referred to as "third interconnects 125") for respectively connecting the first circuit 121 to the first interconnects 123-1 through 123-4. The first interconnects 123 are formed by patterning a first conductive layer, and the second interconnects 124 and the third interconnects 125 are formed by patterning a second conductive layer which is different from the first conductive layer. Each first interconnect 123-1 through 123-4 is connected to a respective second interconnect 124-1 through 124-4 and a respective third interconnect 125-1 through 125-4 through contact holes formed in an insulative layer (not shown). The first interconnects 123 have a smaller resistance and a smaller parasitic capacitance per unit length than the second interconnects 124 and the third interconnects 125.
In such a structure, data is transmitted between one of the second circuit 122-1 through 122-6 and the first circuit 121. For example, when data is transmitted between the second circuit 122-1 and the first circuit 121 as shown in FIG. 6, a data path K1 from an output terminal C1 of the second circuit 122-1 to the first circuit 121 is formed. The data path K1 includes one of the second interconnects 124 (represented by reference numeral 124-1), a portion 123a of one of the first interconnects 123 (represented by reference numeral 123-1), and one of the third interconnects 125 (represented by reference numeral 125-1). The data path K1 has at least a resistance and a parasitic capacitance of its own. Since the data path K1 is connected to the second interconnects 124 of the other second circuits 122-2 through 122-6, the parasitic capacitances of the other second circuits 122-2 through 122-6 are applied to the data path K1.
In a similar manner, when one of the other second circuits 122-2 through 122-6 is connected to the first circuit 121, a data path from an output terminal of that second circuit to the first circuit 121 has a resistance and a parasitic capacitance of its own as well as parasitic capacitances of the other second circuits which are connected to a corresponding data path.
The second interconnects 124 and the third interconnects 125 have larger interconnect resistances and larger parasitic capacitances than those of the first interconnects 123. Accordingly, when the total length of the second interconnects 124 and the third interconnect 125 connected to the data path K1 changes, the delay time period also changes.
In the circuit configuration shown in FIG. 5, the second circuits 122-1 through 122-6 are away from the first interconnect 123 by an equal distance. The second interconnect 124-1 is the shortest and connects an output terminal C1 of each of the second circuits 122-1 through 122-6 to the first interconnect 123-1. The lengths of the second interconnects 124 increase in the following order, as can be seen from FIGS. 5 and 6: the second interconnect 124-2 for connecting an output terminal C2 of each of the second circuits 122-1 through 122-6 to the first interconnect 123-2, the second interconnect 124-3 for connecting an output terminal C3 of each of the second circuits 122-1 through 122-6 to the first interconnect 123-3, and the second interconnect 124-4 for connecting an output terminal C4 of each of the second circuits 122-1 through 122-6 to the first interconnect 123-4. Accordingly, second interconnects 124 having different lengths are connected to different first interconnects 123. The length of the second interconnects 124 connected to the data path changes in accordance with which of the first interconnects 123 forms the data path. The delay time period also changes accordingly.
The change in the length of the second interconnects 124 connected to the data path and the accompanying change in the delay time period are determined based on expression (2), as described below.
Referring to FIG. 6, the data path K1 is formed from the output terminal C1 of the second circuit 122-1 to the first circuit 121. As described above, the data path K1 includes the second interconnect 124-1, a portion 123a of the first interconnect 123-1, and the third interconnect 125-1. Where the length of the first interconnect 123-1 is M, the length of the portion 123a is M.sub.K1, the resistance of the first interconnect 123-1 per unit length is R0.sub.M, and the capacitance of the first interconnect 123-1 per unit length is C0.sub.M ; the delay time period caused by the portion 123a of the first interconnect 123-1 is M.sub.K1 .multidot.R0.sub.M .multidot.M.multidot.C0.sub.M. The sum of length L1 of the second interconnect 124-1 and length L5 of the third interconnect 125-1 is L.sub.K1. The total length of the second interconnects 124-1 of the second circuit 122-2 through 122-6 which are connected to the data path K1 is L1.multidot.5. The resistance of the second interconnects 124 and the third interconnects 125, connected to the data path K1, per unit length is R0.sub.L, and the capacitance of the second interconnects 124 and the third interconnects 125, connected to the data path K1, per unit length is C0.sub.L. The delay time period caused by the second interconnects 124 and the third interconnects 125 is L.sub.K1 .multidot.R0.sub.L .multidot.(L.sub.K1 +L1.multidot.5).multidot.C0.sub.L. Accordingly, delay time period TA1c1 of the entire data path K1 is represented by expression (3). EQU TA1c1=M.sub.K1 .multidot.R0.sub.M .multidot.M.multidot.C0.sub.M +L.sub.K1 .multidot.R0.sub.L .multidot.(L.sub.K1 +L1.multidot.5).multidot.C0.sub.L(3 )
The data paths K2, K3 and K4 can be formed respectively from the output terminals C2, C3 and C4 of the second circuit 122-1 to the first circuit 121. Respective delay time periods TA1c2, TA1c3 and TA1c4 are represented by expressions (4), (5) and (6). EQU TA1c2=M.sub.K1 .multidot.R0.sub.M .multidot.M.multidot.C0.sub.M +L.sub.K1 .multidot.R0.sub.L .multidot.(L.sub.K1 +L2.multidot.5).multidot.C0.sub.L(4 ) EQU TA1c3=M.sub.K1 .multidot.R0.sub.M .multidot.M.multidot.C0.sub.M +L.sub.K1 .multidot.R0.sub.L .multidot.(L.sub.K1 +L3.multidot.5).multidot.C0.sub.L(5 ) EQU TA1c4=M.sub.K1 .multidot.R0.sub.M .multidot.M.multidot.C0.sub.M +L.sub.K1 .multidot.R0.sub.L .multidot.(L.sub.K1 +L4.multidot.5).multidot.C0.sub.L(6 )
where L2, L3 and L4 are lengths of the second interconnects 124-2, 124-3 and 124-4.
The difference among the delay time periods TA1c1, TA1c2, TA1c3 and TA1c4 depends on the difference among the lengths L1, L2, L3 and L4 of the second interconnects 124-1, 124-2, 124-3 and 124-4 from the output terminals C1, C2, C3 and C4 of the second circuit 122-1. Since L1&lt;L2&lt;L3&lt;L4, TA1c1&lt;TA1c2&lt;TA1c3&lt;TA1c4.
As can be understood from this, the total length of the second interconnects 124 connected to each of the data paths K1 through K4 changes in accordance with the output terminal of the second circuit 122-1 from which the data is transmitted, and thus the delay time period also changes. This is applied to the other second circuits 122-2 through 122-6. Since the second interconnect 124-4 from the output terminal C4 is longest, the delay time period is longest when the data is output from the output terminal C4.
In order to shorten the delay time period, the second interconnect 124-4 from the output terminal C4 can be connected to one of the first interconnects 123 which is closer to the first circuit 121. However, this causes one of the other second interconnects 124 to be connected to the first interconnect 123 farther from the first circuit 121. Accordingly, the total delay time period of the circuit configuration is not shortened. Conventionally, accumulation of such delay time periods prevents higher rate operation of the LSIs and other circuits. The non-uniformity among the delay time periods TA1c1, TA1c2, TA1c3 and TA1c4 is not preferable in terms of stability of circuit operation.